Looking for a Signal Integrity Engineer with experience in the following areas:

1. Timing/Signal analysis for high-speed parallel bus design.
2. Electrical design constraints in chip package design
3. 2D and 3D filed solver
4. Power integrity tool(s)
5. Good communication skills and documentation experience.
6. Knows VNA, probe station, high-BW scope. Lab probing techniques.

Plus to have:
Familiar with SerDes channel design and design tradeoffs with SerDes macro.